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cy8c20234 automotive psoc ? programmable system-on-chip cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-54650 rev. *e revised june 10, 2011 features automotive electronics council (aec) q100 qualified low power capsense ? block ? configurable capacitive sensing elements ? supports combination of capsense buttons, sliders, touch- pads, and proximity sensors powerful harvard-architecture processor ? m8c processor speeds up to 12 mhz ? low power at high speed ? operating voltage: 3.0 v to 5.25 v ? automotive temperature range: ?40 c to +85 c flexible on-chip memory ? 8 kb of flash program stor age, 1000 erase/ write cycles ? 512 bytes of sram data storage ? partial flash updates ? flexible protection modes ? in-system serial programming (issp) complete development tools ? free development tool (psoc designer?) ? full featured, in-circuit em ulator (ice) and programmer ? full-speed emulation ? complex breakpoint structure ? 128 kb trace memory precision, programmable clocking ? internal 5% 6-/12-mhz oscillator ? internal low-speed, low-power oscillator for watchdog and sleep functionality programmable pin configurations ? 20 ma sink on all general purpose i/os (gpios) ? pull-up, high z, open drain, or strong drive modes on all gpios ? up to 13 analog inputs on gpios ? configurable interrupt on all gpios ? selectable, regulated digital i/o on port 1 ? 3.0 v, 2.4 v, and 1.8 v regulation available ? up to 5 ma source on port 1 gpios versatile analog mux ? common internal analog bus ? simultaneous connection of i/o combinations ? comparator noise immunity additional system resources ? configurable communication speeds ?i 2 c? slave operation up to 400 khz ? spi master or slave operation between 46.9 khz and 12 mhz ? watchdog and sleep timers ? internal voltage reference ? integrated supervisory circuit sram 512 bytes system bus interrupt controller 6/12 mhz internal main oscillator global analog interconnect psoc core cpu core (m8c) srom flash 8k system resources analog system analog ref. i2c slave/spi master-slave por and lvd system resets port 1 port 0 sleep and watchdog analog mux port 3 port 2 capsense block config ldo logic block diagram [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 2 of 30 contents psoc? functional overview ........................................... 3 psoc core .................................................................. 3 capsense analog system .......................................... 3 additional system resources ..................................... 4 psoc device characteristics . ..................................... 4 getting started .................................................................. 5 application notes ........................................................ 5 development kits ........................................................ 5 training ....................................................................... 5 cypros consultants .................................................... 5 solutions library .......................................................... 5 technical support ....................................................... 5 development tools .......................................................... 6 psoc designer software subsyst ems .......... .............. 6 designing with psoc designer ....................................... 7 select user modules ................................................... 7 configure user modules .............................................. 7 organize and connect .............. .............. ........... ......... 7 generate, verify, and debug ....................................... 7 pinouts .............................................................................. 8 16-pin part pinout ....................................................... 8 electrical specifications .................................................. 9 absolute maximum ratings .... ................................... 10 operating temperature ............................................. 10 dc electrical characteristics ..................................... 11 ac electrical characteristics ..................................... 14 packaging information ................................................... 18 thermal impedances ................................................. 18 solder reflow specifications ..................................... 18 tape and reel information .... .............. .............. ........ 19 development tool selection .. .............. .............. ........... 20 software .................................................................... 20 development kits ...................................................... 20 evaluation tools ........................................................ 20 device programmers ............. .................................... 21 accessories (emulation and programming) .............. 21 ordering information ...................................................... 22 ordering code definitions ..... .................................... 22 reference information ................................................... 23 acronyms .................................................................. 23 reference documents ............................................... 23 document conventions ......... .................................... 24 glossary .................................................................... 24 document history page ................................................. 29 sales, solutions, and legal information ...................... 30 worldwide sales and design s upport ......... .............. 30 products .................................................................... 30 psoc solutions ......................................................... 30 [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 3 of 30 psoc ? functional overview the psoc family consists of many programmable system-on-chip with on-chip controller devices. these devices are designed to replace multiple traditional microcontroller unit (mcu)-based system components wit h one low cost single chip programmable component. a psoc device includes configurable analog and digi tal blocks and programmable interconnect. this architecture enables the user to create customized peripheral configurat ions to match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the psoc architecture for this device family, as shown in ?logic block diagram? on page 1, consists of three main areas: the psoc core, the system resources, and the capsense analog system. a common versatile bus enables connection between i/o and the analog system. ea ch cy8c20x34 psoc device includes a dedicated capsense blo ck that provides sensing and scanning control circuitry for capacitive sensing applications. depending on the psoc package, up to 13 gpios are also included. the gpios provide access to the mcu and analog mux. psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, internal main oscillator (imo), and internal low-speed oscillator (ilo). the cpu core, called the m8c, is a powerful processor with speeds up to 12 mhz. the m8c is a two-mips, 8-bit harvard- architecture microprocessor. system resources provide additional capability such as a configurable i 2 c slave, spi slave, or spi master communication interface and various system re sets supported by the m8c. the capsense analog system consists of the capsense ? psoc block and an internal analog re ference. together they support capacitive sensing of up to 13 inputs. capsense analog system the capsense analog system contains the capacitive sensing hardware. several hardware algorithms are supported. this hardware performs capacitive sensing and scanning without requiring external components. capacitive sensing is configurable on each gpio pin. scanning of enabled capsense pins is completed quickly and easily across multiple ports. figure 1. analog system block diagram analog multiplexer system the analog mux bus connects to every gpio pin. pins are connected to the bus individually or in any combination. the bus also connects to the analog system for analysis with the capsense block comparator. switch control logic enables selected pins to precharge continuously under hardware control. this enables capacitive measurement for applications such as touch sensing. other multiplexer applications include: complex capacitive sensing inte rfaces such as sliders and touch pads chip-wide mux that enables analog input from any i/o pin crosspoint connection between any i/o pin combination id ac reference buffer vr cinternal analog global bus cap sense counters com parator mux mux refs capsense clock select relaxation o scillator (ro) csclk imo [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 4 of 30 additional system resources system resources provide additional capability useful for complete systems. additional resources include low voltage detection (lvd) and power-on reset (por). brief statements describing the merits of each system resource are presented below. there is a digital module in cy8c20x34 devices that imple- ments an i 2 c slave, spi slave, or spi master interface.the i 2 c slave mode provides 0 to 40 0 khz communication over two wires. the spi master and slave modes provide communi- cation over three or four wires at frequencies of 46.9 khz to 12 mhz (lower for a slower system clock). lvd interrupts signal the application of falling voltage levels, while the advanced por circuit eliminates the need for a system supervisor. an internal voltage reference provides an absolute reference for capacitive sensing. the 3.0-v/2.4-v/1.8-v fixed output, low dropout regulator (ldo) provides regulation for i/os. a register controlled bypass mode enables the user to disable the ldo. psoc device characteristics depending on your psoc device ch aracteristics, the digital and analog systems can have 16, 8, 4, or 0 digital blocks and 12, 6, 4, or 0 analog blocks. the following ta ble lists the resources available for specific ps oc device groups. the device covered by this datasheet is shown in the hi ghlighted row of the table. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 [1] up to 64 4 16 up to 12 4 4 12 2 k 32 k cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12 + 4 [2] 1 k 16 k cy8c27x43 up to 44 2 8 up to 12 4 4 12 256 16 k cy8c24x94 [1] up to 56 1 4 up to 48 2 2 6 1 k 16 k cy8c24x23a [1] up to 24 1 4 up to 12 2 2 6 256 4 k cy8c23x33 up to 26 1 4 up to 12 2 2 4 256 8 k cy8c22x45 up to 38 2 8 up to 38 0 4 6 [2] 1 k 16 k cy8c21x45 up to 24 1 4 up to 24 0 4 6 [2] 512 8 k cy8c21x34 [1] up to 28 1 4 up to 28 0 2 4 [2] 512 8 k cy8c21x23 up to 16 1 4 up to 8 0 2 4 [2] 256 4 k cy8c20x34 [1] up to 28 0 0 up to 28 0 0 3 [2,3] 512 8 k cy8c20xx6 up to 36 0 0 up to 36 0 0 3 [2,3] up to 2 k up to 32 k notes 1. automotive qualified devices available in this group. 2. limited analog functionality. 3. two analog blocks and one capsense ? block. [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 5 of 30 getting started for in depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics an d skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assis- tance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 6 of 30 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can us e to customize psoc to meet your specific application require ments. psoc designer software accelerates system design and ti me to market. develop your applications using a library of pre-characterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated appl ication programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/trans- mitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (d acs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this pre-populates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this allows you to use more than 100 percent of psoc's resources for a given application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows you to create a trac e buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-s ensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulat ion pod takes the place of the psoc device in the target board and performs full-speed (24-mhz) operation. [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 7 of 30 designing with psoc designer the development process for the psoc ? device differs from that of a traditional fixed function mi croprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process is summarized in four steps: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the select ed function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each 8 bits of resolu tion. the user module parameters permit you to establish the pulse width and duty cycle. configure the parameters and properties to corre- spond to your chosen application. enter values directly or by selecting values from drop-dow n menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specificatio ns. each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in either c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems cost ing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface prov ides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 8 of 30 pinouts this section describes, lists, and illustrates the automotive cy8c20x34 psoc device pins and pinout configurations. the automotive cy8c20x34 psoc device is ava ilable in the packages listed and shown in the following tables. every port pin (lab eled with a ?p?) is capable of digital i/o and can connect to the common analog bus. however, v ss , v dd , and xres are not capable of digital i/o. 16-pin part pinout figure 2. cy8c20234 16-pin psoc device table 2. pin definitions ? cy8c20234 16-pin (qfn) pin no. type name description digital analog 1 i/o i p2[5] 2 i/o i p2[1] 3 i/oh i p1[7] i 2 c serial clock (scl), spi slave select (ss) 4 i/oh i p1[5] i 2 c serial data (sda), spi master-in-slave-out (miso) 5 i/oh i p1[3] spi serial clock (sclk) 6 i/oh i p1[1] issp-sclk [4] , i 2 c serial clock (scl), spi master-out-slave-in (mosi) 7 power v ss ground connection 8 i/oh i p1[0] issp-sdata [4] , i 2 c serial data (sda) 9 i/oh i p1[2] 10 i/oh i p1[4] optional external clock (extclk) input 11 input xres active high external reset with internal pull-down 12 i/o i p0[4] 13 power v dd supply voltage 14 i/o i p0[7] 15 i/o i p0[3] integrating input 16 i/o i p0[1] a = analog, i = input, o = output, oh = 5 ma high output drive p0[1], ai v dd p0[7], ai p0[3], ai 16 15 14 13 12 11 10 9 5 6 7 8 1 2 3 4 qfn spi sclk, ai, p1[3] i2c sda, ai, p1[0] v ss i2c scl, spi mosi, ai, p1[1] p0[4], ai p1[2], ai p1[4], ai, extclk xres ai, p2[5] i2c sda, spi miso, ai, p1[5] i2c scl, spi ss, ai, p1[7] ai, p2[1] note 4. these are the issp pins, that are not high z after exiting a reset state. see the psoc technical reference manual for cy8c20x34 devices for details. [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 9 of 30 electrical specifications this section presents the dc and ac electr ical specifications of the automotive cy8c20x34 psoc device. for the latest electrica l specifications, check the most recent data sheet by visiting the web at http://www.cypress.com . specifications are valid for ?40 c t a 85 c and t j 100 c as specified, except where mentioned. refer to table 11 on page 14 for the electrical specifications on the imo using slimo mode. figure 3. voltage versus cpu frequency figure 4. imo frequency trim options 5.25 4.75 750 khz cpu frequency (nominal setting) v dd voltage (v) 0 3.0 6 mhz 12 mhz 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=0 slimo mode=0 slimo mode=1 5.25 4.75 6 mhz 12 mhz imo frequency v dd voltage (v) 0 3.0 3.6 slimo mode=1 [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 10 of 30 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature table 3. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. time spent in storage at a temperature greater than 65 c counts toward the flash dr electrical specification in table 10 on page 13 . t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tri-state v ss ? 0.5 ? v dd + 0.5 v i mio maximum current in to any port pin ?25 ? +50 ma esd electrostatic discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma table 4. operating temperature symbol description min typ max units notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. see table 19 on page 18 . the user must limit the power consumption to comply with this requirement. [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 11 of 30 dc electrical characteristics dc chip level specifications ta b l e 5 lists the guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical paramete rs apply to 5 v or 3.3 v at 25 c. these are for design guidance only. dc gpio specifications ta b l e 6 lists the guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c. these are for design guidance only. table 5. dc chip level specifications symbol description min typ max units notes v dd supply voltage 3.0 ? 5.25 v see table 8 on page 12 . i dd12 supply current, imo = 12 mhz ? 1.5 2.5 ma conditions are v dd = 3.0 v, t a = 25 c, cpu = 12 mhz. i dd6 supply current, imo = 6 mhz ? 1 1.5 ma conditions are v dd = 3.0 v, t a = 25 c, cpu = 6 mhz i sb sleep (mode) current with por, lvd, sleep timer, wdt, and ilo active. ? 2.8 5 a v dd = 3.3 v, ?40 c t a 85 c table 6. dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k r pd internal pull-down resistor on xres pin 4 5.6 8 k v oh1 high output voltage port 0, 2, or 3 pins v dd ? 0.2 ??vi oh 10 a, v dd 3.0 v, maximum of 20 ma source current in all i/os. v oh2 high output voltage port 0, 2, or 3 pins v dd ? 0.9 ??vi oh 1 ma, v dd 3.0 v, maximum of 20 ma source current in all i/os. v oh3 high output voltage port 1 pins with ldo disabled v dd ? 0.2 ??vi oh 10 a, v dd 3.0 v, maximum of 10 ma source current in all i/os. v oh4 high output voltage port 1 pins with ldo disabled v dd ? 0.9 ??vi oh 5 ma, v dd 3.0 v, maximum of 20 ma source current in all i/os. v oh5 high output voltage port 1 pins with 3.0-v ldo enabled 2.7 3.0 3.3 v i oh 10 a, v dd 3.1 v, maximum of 4 i/os all sourcing 5 ma. v oh6 high output voltage port 1 pins with 3.0-v ldo enabled 2.2 ? ? v i oh 5 ma, v dd 3.1 v, maximum of 20 ma source current in all i/os. v oh7 high output voltage port 1 pins with 2.4-v ldo enabled 2.1 2.4 2.7 v i oh 10 a, v dd 3.0 v, maximum of 20 ma source current in all i/os. v oh8 high output voltage port 1 pins with 2.4-v ldo enabled 2.0 ? ? v i oh 200 a, v dd 3.0 v, maximum of 20 ma source current in all i/os. v oh9 high output voltage port 1 pins with 1.8-v ldo enabled 1.6 1.8 2.0 v i oh 10 a 3.0 v v dd 3.6 v 0 c t a 85 c maximum of 20 ma source current in all i/os. v oh10 high output voltage port 1 pins with 1.8-v ldo enabled 1.5 ? ? v i oh 100 a. 3.0 v v dd 3.6 v. 0 c t a 85 c. maximum of 20 ma source current in all i/os. [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 12 of 30 dc analog mux bus specifications ta b l e 7 lists the guaranteed maximum and minimum specifications for t he voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c. these are for design guidance only. dc por and lvd specifications ta b l e 8 lists the guaranteed maximum and minimum specifications for t he voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c. these are for design guidance only. v ol low output voltage ? ? 0.75 v i ol 20 ma, v dd 3.0 v, maximum of 60 ma sink current on even port pins (for example, p0[4] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]). v il input low voltage ? ? 0.8 v v ih input high voltage 2.0 ? v v h input hysteresis voltage ? 140 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent t a = 25 c c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent t a = 25 c table 6. dc gpio specifications (continued) symbol description min typ max units notes table 7. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 450 table 8. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 v dd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 2.36 2.60 2.82 2.40 2.65 2.95 v v v v dd must be greater than or equal to 2.5 v during startup, reset from the xres pin, or reset from watchdog. v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.34 2.54 2.75 2.85 2.96 ? ? 4.44 2.45 2.71 2.92 3.02 3.13 ? ? 4.73 2.51 [5] 2.78 [6] 2.99 [7] 3.09 3.20 ? ? 4.93 v v v v v v v v notes 5. always greater than 50 mv above v ppor (porlev = 00) for falling supply. 6. always greater than 50 mv above v ppor (porlev = 01) for falling supply. 7. always greater than 50 mv above v ppor (porlev = 10) for falling supply. [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 13 of 30 dc analog reference specifications ta b l e 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c. these are for design guidance only. dc programming specifications ta b l e 1 0 lists the guaranteed minimum and maximu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c. these are for design guidance only. flash endurance and retention specif ications with the use of the ee prom user module are valid onl y within the range: 25 c 20 c during the flash write operation. refer to the eeprom user module data sheet instructions for eeprom flash write requirement s outside of the 25 c 20 c temperature window. table 9. dc analog reference specifications symbol description min typ max units notes bg bandgap reference voltage 1.274 1.30 1.326 v notes 8. the erase/write cycle limit per block (flash enpb ) is only guaranteed if the device operates within one voltage ra nge. voltage ranges are 3.0 v to 3.6 v and 4.75 v to 5.25 v. 9. the maximum total number of allowed erase/write cycles is the minimum flash enpb value multiplied by the number of flash blocks in the device. table 10. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5 5.5 v this specification applies to the functional requirements of external programmer tools v ddlv low v dd for verify 3.0 3.1 3.2 v this specification applies to the functional requirements of external programmer tools v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools v ddiwrite supply voltage for flash write operation 3.0 ? 5.25 v this specification applies to this device when it is executing internal flash writes i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) [8] 1,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) [9] 128,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 14 of 30 ac electrical characteristics ac chip level specifications ta b l e 11 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c. these are for design guidance only. table 11. ac chip-level specifications symbol description min typ max units notes f cpu1 cpu frequency 0.71 ? 12.6 mhz 12 mhz only for slimo mode = 0 f 32k1 ilo frequency 15 32 64 khz this specification applies when the ilo has been trimmed. f 32ku ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c processor starts to execute, the ilo is not trimmed. f imo12 imo frequency for 12 mhz 11.4 12 12.6 mhz trimmed using factory trim values. see figure 4 on page 9 , slimo mode = 0. f imo6 imo frequency for 6 mhz 5.5 6.0 6.5 mhz trimmed using factory trim values. see figure 4 on page 9 , slimo mode = 1. dc imo imo duty cycle 40 50 60 % dc ilo ilo duty cycle 20 50 80 % t xrst external reset pulse width 10 ? ? s sr powerup power supply slew rate ? ? 250 v/ms v dd slew rate during power-up. t powerup time between end of por state and cpu code execution ? 16 100 ms power-up from 0 v. t jit_imo [10] 12 mhz imo cycle-to-cycle jitter (rms) ? 200 1600 ps 12 mhz imo long-term n cycle-to-cycle jitter (rms) ? 600 1400 ps n = 32 12 mhz imo period jitter (rms) ? 100 900 ps note 10. refer to cypress jitter specifications application note ? an5054 at http://www.cypress.com for more information. [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 15 of 30 ac gpio specifications ta b l e 1 2 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c. these are for design guidance only. figure 5. gpio timing diagram ac comparator specifications ta b l e 1 3 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c. these are for design guidance only. ac external clock specifications ta b l e 1 4 lists the guaranteed maximum and minimu m specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c. these are for design guidance only. table 12. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 6.30 mhz normal strong mode, port 1. t rise023 rise time, strong mode, cload = 50 pf ports 0, 2, 3 15 ? 80 ns v dd = 3.0 v to 3.6 v and 4.75 v to 5.25 v, 10% - 90% t rise1 rise time, strong mode, cload = 50 pf port 1 10 ? 50 ns v dd = 3.0 v to 3.6 v, 10% - 90% t fall fall time, strong mode, cload = 50 pf all ports 10 ? 50 ns v dd = 3.0 v to 3.6 v and 4.75 v to 5.25 v, 10% - 90% tfall trise023 trise1 90% 10% gpio pin output voltage t fall t rise1 t rise023 table 13. ac comparator specifications symbol description min typ max units notes t comp comparator response time, 50 mv overdrive ? ? ? ? 100 200 ns ns v dd > 3.6 v 3.0 v v dd 3.6 v table 14. ac external clock specifications symbol description min typ max units notes f oscext frequency 0.750 ?12.6mhz ? high period 38 ? 5300 ns ? low period 38 ? ?ns ? power-up imo to switch 150 ? ? s [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 16 of 30 ac programming specifications ta b l e 1 5 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c. these are for design guidance only. ac spi specifications table 16 and table 17 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c. these are for design guidance only. table 15. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 40 ms t write flash block write time ? 40 160 ms t dsclk data out delay from falling edge of sclk ? ? 45 ns v dd > 3.6 v t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 v v dd 3.6 v t prgh total flash block program time (t eraseb + t write ), hot ? ? 100 ms t j 0 c t prgc total flash block program time (t eraseb + t write ), cold ? ? 200 ms t j < 0 c table 16. spi master ac specifications symbol parameter min typ max units notes f sclk sclk clock frequency ? ? 12.6 mhz dc sclk sclk duty cycle ?50 ?% t setup miso to sclk setup time 40 ? ?ns t hold sclk to miso hold time 40 ? ?ns t out_val sclk to mosi valid time ? ?40ns t out_high mosi high time 40 ? ?ns table 17. spi slave ac specifications symbol parameter min typ max units notes f sclk sclk clock frequency ? ?12.6mhz t low sclk low time 39.6 ? ?ns t high sclk high time 39.6 ? ?ns t setup mosi to sclk setup time 30 ? ?ns t hold sclk to mosi hold time 50 ? ?ns t ss_miso ss low to miso valid ? ?153ns t sclk_miso sclk to miso valid ? ?125ns t ss_high ss high time 50 ??ns t ss_sclk time from ss low to first sclk 2/f sclk ? ?ns t sclk_ss time from last sclk to ss high 2/f sclk ? ?ns [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 17 of 30 ac i 2 c specifications ta b l e 1 8 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c. these are for design guidance only. figure 6. definition for timing for fast/standard mode on the i 2 c bus table 18. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 [11] 0 400 [11] khz t hdstai2c hold time (repeated) start c ondition. after this period, the first clock pulse is generated 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ?100 [12] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter ? ?050ns notes 11. f scli2c is derived from sysclk of the psoc. this specification assumes that sysclk is operating at 12 mhz, nominal. if sysclk is at a lower frequency, then the f scli2c specification adjusts accordingly. 12. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but t he requirement t sudati2c 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl si gnal. if such device does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t sudati2c = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 18 of 30 packaging information this section illustrates the packaging spec ifications for the automotive cy8c20x34 psoc device along with the thermal impedance s for each package. important note emulation tools may require a larger area on the target pcb than the chip's footprint. fo r a detailed description of the emulation tools' dimensions, refe r to the emulator pod drawings at http://www.cypress.com . for information on the preferred dimensions for mounting qfn pa ckages, see the application note ?application notes for surface mount assembly of amkor's microleadframe (mlf) packages? available at http://www.amkor.com. figure 7. 16-pin (3 3 0.60 mm) qfn (sawn) thermal impedances ta b l e 1 9 illustrates the minimum solder reflow peak temperature to achieve good solderability. solder reflow specifications ta b l e 2 0 shows the solder reflow temperature limits that must not be exceeded. 001-09116 *e table 19. thermal impedances per package package typical ja [12] 16-pin qfn 46 c/w table 20. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 16-pin qfn 260 c 30 seconds note 12. t j = t a + power ja [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 19 of 30 tape and reel information figure 8. 16-pin qfn carrier tape drawing 001-11785 ** all dimensions ar e in millimeters table 21. tape and reel specifications package cover tape width (mm) hub size (inches) minimum leading empty pockets minimum trailing empty pockets standard full reel quantity 16-pin qfn 9.2 7 63 38 2500 [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 20 of 30 development tool selection this section presents the development tools av ailable for the automotive cy8c20x34 family. software psoc designer at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is available free of charge at http://www.cypress.com and includes a free c compiler. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory programming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer or psoc express. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com . development kits all development kits c an be purchased from the cypress online store . the online store also has the most up to date information on kit contents, descriptions, and availability. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. psoc designer also supports the advance emulation features. the kit includes: ice-cube unit 28-pin pdip emulation pod for cy8c29466-24pxi 28-pin cy8c29466-24pxi pdip psoc device samples (two) psoc designer software cd issp cable minieval socket programming and evaluation board backward compatibility cable (for connecting to legacy pods) universal 110/220 power supply (12 v) european plug adapter usb 2.0 cable getting started guide development kit registration form cy3280-bk1 the cy3280-bk1 universal capsense control kit is designed for easy prototyping and debug of capsense designs with pre defined control circuitry and plug -in hardware. the kit comes with a control boards for cy8c20x34 and cy8c21x34 devices as well as a breadboard module and a button(5)/slider module. evaluation tools all evaluation tools can be purchased from the cypress online store . the online store also has the most up to date information on kit contents, descripti ons, and availability. cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, an rs-232 port, and plenty of breadboarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3210-20x34 evaluation pod (evalpod) psoc evalpods are pods that c onnect to the ice in-circuit emulator (cy3215-dk kit) to allow debugging capability. they can also function as a standalone device without debugging capability. the evalpod has a 28-pin dip footprint on the bottom for easy connection to development kits or other hardware. the top of the evalpod has prototyp ing headers for easy connection to the device's pins. cy3210-20x34 provides evaluation of the cy8c20x34 psoc device family. [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 21 of 30 device programmers all device programmers are purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industria l case that is more robust than the miniprog in a production-programming environment. note cy3207issp needs special software and is not compatible with psoc programmer. this software is free and can be downloaded from http://www.cypress.com . the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, euro-plug adapter usb 2.0 cable accessories (emula tion and programming) table 22. emulation and programming accessories part number pin package pod kit [13] foot kit [14] prototyping module adapter [15] cy8c20234-12lkxa 16-pin qfn ? ? cy3210-20x34 ? notes 13. pod kit contains an emulation pod, a flex-cable (connects the pod to t he ice), two feet, and device samples. 14. foot kit includes surface mount feet that is soldered to the target pcb. 15. programming adapter converts non-dip package to dip footprint. specific details and ordering information for each of the ada pters is found at http://www.emulation.com . [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 22 of 30 ordering information ta b l e 2 3 lists the automotive cy8c20x34 psoc device key package features and ordering codes. ordering code definitions table 23. psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) digital blocks capsense blocks digital i/o pins analog inputs analog outputs xres pin 16-pin (3 3 0.6 mm) qfn, sawn cy8c20234-12lkxa 8 k 512 0 1 13 13 0 yes 16-pin (3 3 0.6 mm) qfn, sawn (tape and reel) CY8C20234-12LKXAT 8 k 512 0 1 13 13 0 yes cy 8 c 20 xxx- 12 xx package type: thermal rating: px = pdip pb-free a = automotive ?40 c to +85 c sx = soic pb-free c = commercial pvx = ssop pb-free e = automotive extended ?40 c to +125 c lfx/lkx = qfn pb-free i = industrial ax = tqfp pb-free cpu speed: 12 mhz part number family code technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 23 of 30 reference information acronyms ta b l e 2 4 lists the acronyms that are used in this document. reference documents psoc ? cy8c20x34 and psoc? cy8c20x24 technical reference manual (trm) (001-13033) understanding datasheet jitter specifications for cypress timing products ? an5054 (001-14503) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . table 24. acronyms used in this datasheet acronym description acronym description ac alternating current lvd low voltage detect adc analog-to-digital converter mcu microcontroller unit aec automotive electronics council mi ps million instructions per second api application programming interface pcb printed circuit board cmos complementary metal oxide semiconductor pdip plastic dual inline package cpu central processing unit pga programmable gain amplifier dac digital-to-analog converter por power-on reset dc direct current ppor precision (por) eeprom electrically erasable programmable read-only memory psoc ? programmable system-on-chip gpio general-purpose i/o pwm pulse-width modulator i/o input/output qfn quad flat no leads ice in-circuit emulator rms root mean square ide integrated development environment slimo slow imo ilo internal low-speed oscillator spi serial peripheral interface imo internal main oscillator s ram static random-access memory issp in-system serial programming srom supervisory read-only memory lcd liquid crystal display usb universal serial bus ldo low dropout regulator wdt watchdog timer led light-emitting diode xres external reset [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 24 of 30 document conventions units of measure ta b l e 2 5 lists the units of measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 25. units of measure symbol unit of measure symbol unit of measure c degree celsius mv millivolt kb 1024 bytes na nanoampere khz kilohertz ns nanosecond k kilohm ohm mhz megahertz % percent a microampere pf picofarad s microsecond ps picosecond ma milliampere v volt mm millimeter w watt ms millisecond glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. api (application programming interface) a series of software routines that comprise an interface between a computer application and lower level services and functions (for exampl e, user modules and libraries). apis serve as building blocks for programmers that create softwa re applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 25 of 30 block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perfo rm one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; fo r example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed frequen cy and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in whic h the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient te mperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data co mmunications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a comp uter to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allows the user to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter pe rforms the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. glossary (continued) [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 26 of 30 emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technol ogy that provides users with the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be pr otected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, vo ltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5 v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode an d 400 kbits/second in fast mode. ice the in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the ex ecution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exis t with its own priority and individual isr code block. each isr code block ends with the reti in struction, returning t he device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls below a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the fl ash, sram, and register space. master device a device that controls the timing for da ta exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external in terface. the controlled device is called the slave device . glossary (continued) [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 27 of 30 microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a co ntroller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation bet ween the logical inputs and outputs of the psoc device and their physical counterparts in t he printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is below a pre-set level. this is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. glossary (continued) [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 28 of 30 settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device t hat sequentially shifts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, th e slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory . a memory device allowing users to store and retrieve data at a high rate of speed. the term static is used because, after a value has been loaded into an sram cell, it remains unchanged un til it is explicitly altered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output ca n adopt three states: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowin g another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. glossary (continued) [+] feedback
cy8c20234 document number: 001-54650 rev. *e page 29 of 30 document history page document title: cy8c20234 automotive psoc ? programmable system-on-chip document number: 001-54650 revision ecn orig. of change submission date description of change ** 2743436 masj/aesa 07/24/09 new data sheet. *a 2799448 btk 11/05/09 updated features section. updated text of psoc functional overview section. updated getting started sectio n. made corrections and minor text edits to pinouts section. changed the name of some sections to improve consistency. added clarifying comments to some electrical specifications. fixed all ac specifications to conf orm to a 5% imo accuracy. made other miscellaneous minor text edits. deleted some non-applicable or redundant information. improved and edited conten t in development tool selection section. improved the bookma rk structure. changed flash ent , f oscext , t eraseb , and t write electrical specifications according to masj input. added and slightly modified the expanded spi ac specifications from 001-05356 rev *i. added a table of contents. *b 2822792 btk/aesa 12/07/2009 added t prgh, t prgc, f 32ku , dc ilo , and t powerup electrical specifications. updated the footnotes for table 10, ?dc programming specifications,? on page 13. added maximum values and updated typical values for t eraseb and t write electrical specifications. replaced t ramp electrical specification with sr powerup electrical specification. changed f imo6 electrical specifi- cation to have an 8.33% accuracy instead of 5%. added ?contents? on page 2. *c 2888007 njf 03/30/2010 updated cypress website links. updated capsense analog system . removed psoc designer 4.4 reference in psoc designer software subsystems . added t baketemp and t baketime parameters in absolute maximum ratings . removed dc low power comparator specifications, ac analog mux bus specifications, and ac low powe r comparator specifications. updated packaging information . added solder reflow peak temperature . removed third party tools and build a psoc emulator into your board. updated links in sales, solutions, and legal information . *d 3043236 arvm 09/30/10 under section ?ac comparator amplifier specifications?, the caption for spec table changed from ?ac operational amplifier specifications? to ?ac comparator specifications?. also the section heading changed to ac comparator specifications. *e 3272879 btk/njf 06/10/11 updated i 2 c timing diagram to improve clarity. added v ddp , v ddlv , and v ddhv electrical specifications to give more infor- mation for programming the device. updated solder reflow temperature specifications to give more clarity. updated the jitter specifications. added psoc device characteristics table. updated the f 32ku electrical specification. added r pd electrical specification. updated note for the t stg electrical specification to add more clarity. updated units of measure, acronyms, glossary, and references sections. added tape and reel specifications section. [+] feedback
document number: 001-54650 rev. *e revised june 10, 2011 page 30 of 30 all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c20234 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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